Field of the Invention
An aspect of the present invention relates to a nonvolatile semiconductor memory element, nonvolatile semiconductor memory, and a method for operating the nonvolatile semiconductor memory element.
Description of the Related Art
A nonvolatile semiconductor memory element has a structure wherein a tunnel insulating film, a charge storage layer, an upper insulating layer and a control gate are deposited on a semiconductor substrate. The charge storage layer may be formed of a conductive charge storage layer or may be formed of a non-conductive charge storage layer. In the description to follow, the nonvolatile semiconductor memory element using the conductive charge storage layer will be discussed as the floating gate type and the nonvolatile semiconductor memory element using the non-conductive charge storage layer will be discussed as the floating trap type.
With miniaturization (finer design rules) of the nonvolatile semiconductor memory, it is necessary to make the upper insulating layer thinner. Problems introduced as the upper insulating layer becomes thinner will be discussed separately for the floating gate type and the floating trap type.
In the floating gate type, with the upper insulating layer made thinner, the leak current from the conductive charge storage layer at the writing operation is increased and it is made difficult to store a charge. On the other hand, in the floating trap type, with the upper insulating layer made thinner, at the erasing operation, electron injection from the control gate into the charge storage layer is increased and the erasing efficiency is degraded.
Thus, with the upper insulating layer made thinner, the leak current characteristic is increased and the write operation in the floating gate type and the erasing operation in the floating trap type are degraded. Thus, an upper insulating layer having a lower leak current characteristic than that of former structure is required. The leak current characteristic can be decreased by adopting a structure for trapping an electron in the upper insulating layer.
To adopt the structure for trapping an electron in the upper insulating layer, while decreasing the leak current, there is a problem in that the electron trapped at the write operation, the read operation, or the erasing operation is emitted during the data retaining time and causes threshold fluctuation of the nonvolatile semiconductor memory element. JP-2007-193862-A discloses an art of suppressing emission of the electron trapped in the upper insulating layer during the data retaining time. In JP-2007-193862-A, a detrap pulse is applied after data is written into a nonvolatile semiconductor memory element. The detrap pulse is applied, whereby the charge trapped in the upper insulating layer at the write operation can be pulled out, so that charge emission from the upper insulating layer to the charge storage layer at the data retaining time can be suppressed and threshold fluctuation of the nonvolatile semiconductor memory element can be suppressed. The detrap pulse is applied, whereby charge emission from the upper insulating layer to the charge storage layer at the data retaining time can be suppressed and threshold fluctuation of the nonvolatile semiconductor memory element can be suppressed.
In the art, the inventor of the invention focused attention on the fact that while the charge can be pulled out from the upper insulating layer to the charge storage layer at the detrap pulse, a charge from the control gate may be trapped in the upper insulating layer and consequently the charge trapped in the upper insulating layer cannot sufficiently be pulled out. Consequently, the inventor found that there is a possibility that threshold fluctuation of the nonvolatile semiconductor memory element caused by charge emission from the upper insulating layer to the charge storage layer at the data retaining time cannot sufficiently be suppressed.